As is well known in the art of logic circuit design, emitter-coupled logic (ECL), used as a design format for some logic circuits utilizing bipolar transistors, has a counterpart known as source-coupled FET logic (SCFL), which utilizes field effect transistors. In SCFL circuits, several different voltage level outputs are commonly generated for use in subsequent logic circuits. In high-speed SCFL circuits, as in many other high-speed logic circuits, the ability to drive output signals to their nominal levels within the shortest possible time period under a variety of load conditions is important.
For this reason, push-pull output stages have been developed, in which a transitioning output signal is simultaneously used to open one transistor conduction path between the load and a first reference voltage, such as a supply voltage V.sub.DD, and to close another transistor conduction path between the load and a second reference voltage, such as ground. While conventional push-pull output stages have increased output slew rates of SCFL circuits, further improvement in output slew rate is desirable, particularly under heavy load conditions, without increasing the power dissipation of the circuit.